Non-volatile memory with error correction for page copy operation and method thereof

ABSTRACT

The disclosure is a NAND flash memory with the function of error checking and correction during a page copy operation. The NAND flash memory is able to prohibit transcription of erroneous bits to a duplicate page from a source page. Embodiments of the inventive flash memory include a correction circuit for correcting bit errors of source data stored in a page buffer, a circuit configured to provide the source data to the correction circuit and to provide correction data to the page buffer, and a copy circuit configured to copy the source data to the page buffer, and to store the correction data in the other page from the page buffer.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a Continuation of U.S. patent application Ser. No.10/817,061, filed Apr. 2, 2004, now pending, which claims priority fromKorean Patent Application No. 2003-21114, filed Apr. 3, 2003, thecontents of which are herein incorporated by reference in theirentirety.

FIELD OF THE INVENTION

This disclosure generally relates to nonvolatile flash memories and morespecifically, to flash memories for reliable page copy operations witherror correcting functions and their methods of operating therein.

BACKGROUND OF THE INVENTION

Flash memories are commonly applicable to mass storage subsystems forelectronic devices employed in mobile communications, game sets, and soforth. Such subsystems are usually implemented as either removablememory cards that can be inserted into multiple host systems or asnon-movable embedded storage within the host systems. In bothimplementations, the subsystem includes one or more flash devices andoften a subsystem controller.

Flash memories are composed of one or more arrays of transistor cells,each cell capable of non-volatile storage of one or more bits of data.Therefore, flash memories do not require power to retain the dataprogrammed therein. Once programmed however, a cell must be erasedbefore it can be reprogrammed with a new data value. These arrays ofcells are partitioned into groups to provide for efficientimplementation of read, program and erase functions. The typical flashmemory architecture for mass storage arranges large groups of cells intoerasable blocks. Each block is further partitioned into one or moreaddressable sectors that are the basic unit for read and programfunctions.

Flash memories basically have their own functional operations ofreading, writing (or programming), and erasing. Flash memoriesadditionally extend their facilities to practice a page copy operation(or a copy-back operation). The page copy operation is to transcriptdata stored in a page assigned to a specific address to another pageassigned to another address. During the page copy, data stored in a pageof a specific address are transferred to a page buffer and then the dataremaining in the page buffer are written into another page assigned toanother address by way of a programming process without reading the dataout of the flash memory. The page copy function eliminates a need ofreading-out data to be written and of loading data to be written fromthe external source of the flash memory, which is advantageous toenhancing systemic data rates associated with the subsystem controller.

However, unfortunately, it may occur that the pages to be copied and tobe written have their own error bits. As shown in FIG. 1, assuming thata page PG4 is to be copied and a page PGn-3 is to be written, both pageseach having one error bit, the data stored in the page PG4 istransferred to the page buffer 10 and then written into the page PGn-3from the page buffer 10. As a result of the page copy operation, twoerror bits are included in the page PGn-3. Because most flash memorycontrollers used as subsystem controllers in a card-type memory areusually only designed to correct one-bit error for a page, such atwo-bit error in a page may be incapable of being cured after completingthe copy back operation.

Although a flash memory controller could be equipped with an errorcorrecting function capable of coping even with the two-bit error perpage, it would cause the circuit architecture to be much more complexand thereby deteriorate operational efficiencies in the memory controlsystem.

Embodiments of the invention address these and other limitations of theprior art.

SUMMARY OF THE INVENTION

Embodiments of the present invention provide a nonvolatile memorycapable of maintaining the integrity of data through a page copyoperation, and a method thereof. Such a nonvolatile memory is capable ofpreventing a transcription of error bits during a page copy operation.

According to an aspect of the present invention, a nonvolatile memoryincludes a number of pages storing data; a page buffer temporarilystoring data by the page; a circuit for correcting a bit error of sourcedata of a specific one of the pages; circuitry configured to provide thesource data to the circuit and to provide amended data to the pagebuffer from the circuit; and a copy circuit configured to copy thesource data into the page buffer and to store the amended data intoanother page from the page buffer.

The circuit generates new parities from the source data and compares thenew parities with the old parities. Additionally, the device includes acircuit for generating column parities for bits composing one byte ofthe source data; and a circuit for generating line parities for bytes ofthe source data.

In the embodiment, a nonvolatile memory includes: a data field composedof a number of pages for storing data; a first circuit configured tostoring first parities in a predetermined region of the data field, thefirst parities being generated during a programming operation for thepage; a page buffer for temporarily storing data by the page; a secondcircuit configured to copy source data stored in a specific one of thepages into the page buffer; a third circuit configured to generatesecond parities from the source data stored in the page buffer; and afourth circuit configured to transfer amended data of the source data tothe page buffer in response to a result of comparing the first paritieswith the second parities. A fifth circuit is further included to storethe amended data held in the page buffer into another page of the pages.

In the embodiment, a method of transferring source data of a specificpage, the source data containing old parities, to another page in anonvolatile memory having a page buffer temporarily storing data by thepage, includes the processes of: storing the source data into the pagebuffer; generating new parities from the source data stored in the pagebuffer; comparing the old parities with the new parities; creatingmodified data of the source data in response to a result of thecomparing; and moving the modified data to the another page through thepage buffer. From the embodiment, it is available to inform an errorstatus by the comparing result of the outside of the memory.

In this embodiment, a nonvolatile memory includes: a data storage fieldcomposed of a number of pages storing data; a page buffer for storingdata of a specific one of the pages, being connected to the data storagefield; and error correction circuit connected to the page buffer andincluding: a bit error detector configured to detect an bit error of thedata of the specific page; and a bit error corrector configured to amendthe bit error. The bit error detector includes: a parity generator forcreating new parities from the data stored in the page buffer; and acomparator for generating error address information by comparing the newparities with old parities of the data.

The error address information is referred by the bit error corrector tocorrect the data and to transfer amend data to the page buffer. Themodified data are transcribed into the specific page and another page.

The present invention will be better understood from the followingdetailed description of the exemplary embodiment thereof taken inconjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The forgoing and other features and advantages of the invention will beapparent from the more particular description of a preferred embodimentof the invention, as illustrated in the accompanying drawings in whichlike reference characters refer to the same parts throughout thedifferent views. The drawings are not necessarily to scale, emphasisinstead being placed upon illustrating the principles of the invention:

FIG. 1 is a block diagram illustrating a conventional page copy-backfeature in a NAND flash memory device.

FIG. 2 is a block diagram illustrating a page copy-back feature witherror correction according to embodiments of the present invention.

FIG. 3 is a block diagram illustrating an error correction circuitaccording to embodiments of the present invention.

FIG. 4 is a circuit diagram illustrating gating circuits for performingdata transmission between page buffers and the error correction circuitof FIG. 3.

FIG. 5 is a timing diagram of data transmission between the page buffersand the error correction circuit of FIG. 3.

FIG. 6 is a table illustrating a procedure of generating column and lineparities according to embodiments of the invention.

FIG. 7 is a circuit diagram illustrating a circuit for generating thecolumn parities shown in FIG. 6.

FIG. 8 is a circuit diagram illustrating a circuit for generating theline parities shown in FIG. 6.

FIG. 9 is a timing diagram of signals used in data transmission betweenthe page buffers and the error correction circuit.

DESCRIPTION OF THE PREFERRED EMBODIMENT

It should be understood that the description of the preferred embodimentis merely illustrative and that it should not be taken in a limitingsense. In the following detailed description, several specific detailsare set forth in order to provide a thorough understanding of thepresent invention. It will be obvious, however, to one skilled in theart that the present invention may be practiced without these specificdetails.

A flash memory applicable to the present invention is embodied on a NANDflash memory, adaptable to be embedded in portable electronic devicessuch as integrated circuit cards, in which a number of memory cells arearranged in the pattern of strings coupled to a plurality of wordlinesand bitlines disposed in a matrix of rows and columns.

A NAND flash memory according to embodiments of the present inventionhas a memory cell array divided into a plurality of pages designated byaddresses. Each page is formed of a number of memory cells coupled to awordline and coupled to a plurality of bitlines each by each. The pageis a unit of reading and writing.

A NAND flash memory according to embodiments of the present invention isdesigned to carry out functional operations such as erasing to removedata stored in memory cells, programming to write data in memory cells,reading data out of the memory (i.e. a read-out operation), verifying tocheck out the status of memory cells after completing the erasing andprogramming, and page-copying to transcript data of a page into anotherpage without a read-out operation.

A NAND flash memory according to embodiments of the present inventionincludes a page buffer circuit for temporally storing data to be readfrom memory cells or loaded from outside the memory in the operations ofprogramming, reading-out, or page-copying. Also including are buffersand decoders for selecting pages or memory cells with addresses suppliedfrom the outside, sense amplifiers for detecting data values, gatecircuitry for transferring data from/to the memory cell array to/frominput/output channels, and control circuits for managing the operationstherein.

Embodiments of to the present invention include an error correctingoperation associated with the page copy function.

In this embodiment, the term “read-out” is used to identify an operationof reading data out of the memory, i.e. the state that data from memorycells go out of the memory. The term “copy” is used to identify anoperation of transferring data of a specific page into the page buffer,and “transcription” is used to identify an operation of moving the dataheld in the page buffer into another page. Further, “source data” isused to identify data to be copied with an error bit, and “modified (orcorrect or amended) data” is used to identify data to be transcribedwithout any error bit.

Now, practical embodiments of the invention will be explained inconjunction with the drawings FIGS. 2 through 9.

FIG. 2 illustrates a schematic feature of correcting a bit error duringa page copy operation mode according to embodiments of the presentinvention. First, data stored in, for example, the page PG4, i.e., thesource data, are loaded into the page buffer 10 by way of a readoperation (this reading is distinguishable from the read-out operationused elsewhere in the present specification), which is referred as the“copy” operation. The data stored in the page buffer 10, i.e., thesource data of the page PG4 (hereinafter referred as “source page), areput into an error correction circuit 20 to cure an error bit embedded inthe source data before they are written into another page (e.g., PGn-3;hereinafter referred to “transcription page”). The data modified by theerror correction circuit 20 are transferred back into the page buffer 10and then written into the page PGn-3. As a result, the page PGn-3 isrendered to be free from the error bit embedded in the source data,preventing from the transcription of an error bit by the source data.

Even if the page PGn-4 to be transcribed has its own error bit, a knownfunction of error correcting may cure the single bit error thereof Moredetails about the error correcting procedure during the page copyoperation will be described hereinbelow.

FIG. 3 illustrates a functional structure for conducting the errorcorrection during the page copy operation. Referring to FIG. 3, once thesource data De temporally stored in the page buffer 10 are provided tothe error correction circuit 20, a comparator 50 compares old paritiesOP, which have been created during the former programming (or writing)cycle and stored in a predetermined field of the memory, with newparities NP that are generated by a parity generator 40 during the copyoperation. The new parities NP are parity data to be used to correct abit error, i.e., a progressive bit error generated during the page copyoperation with the source data. The old and new parities, OP and NP, aregenerated by the same manner. After comparing the old parities OP withthe new parities NP, an information signal Ae of the page addressinvolved in the progressive bit error is generated from the comparator50. The erroneous address information signal Ae is applied to an errorcorrection logic circuit 60 to cure the bit error. The amended data Dcfrom the error correction logic circuit 60 are transferred to the pagebuffer 10 together with control signals CNT therefrom. More detailsabout the parity generation and comparison is described hereinbelow.

FIG. 4 is a circuit diagram of latching and column-decoding blocksLDB0·LDBm-1, being disposed between the page buffering and sensing logicblock 12 (included in the page buffer 10) and input/output linesI/O0˜I/On-1, for transferring the source and correct data. Referring toFIG. 4, the source data of the source page (e.g., PG4) assigned to aspecific address are transferred to the error correction circuit 20 fromthe page buffering and sensing block 12 through the latching andcolumn-decoding blocks LDB0˜LDBm-1 each corresponding to theinput/output lines I/O0˜I/On-1. The latching and column-decoding blocksLDB0˜LDBm-1 also transfers the amended data Dc provided from the errorcorrection circuit 20 to the transcript page (e.g., PGn-1) through thepage buffering and sensing block 12.

The source data De of the source page PG4 are read by the page bufferingand sensing block 12 and stored in latches LCH0˜LCHn-1 eachcorresponding to the bitlines BL0˜BLn-1. The source data staying at thelatches LCH0˜LCHn-1 are transferred to the input/output linesI/O0˜I/On-1 through column gates (or Y-gates) AG0˜AGn-1 and BG0˜BGk-1 inresponse to column gating signals YA0˜YAn-1 (primary) and YB0˜YBk-1(secondary) by a unit of bit sequentially, as shown in FIG. 5, which maybe referred to as “error-data out” as an operational state. Forinstance, a source data bit corresponding to the bitline BL0 istransferred to the error correction circuit 20 through the input/outputline I/O0 when both of the column gating signals YA0 and YB0 are activewith high levels.

The amended data Dc are transferred through the input/output linesI/O0˜I/On-1 from the error correction circuit 20 to the latchesLCH0˜LCHn-1 each coupled to the bitlines BL0˜BLn-1, which may bereferred to as “amended-data in” as an operational state. For instance,an amended data bit corresponding to the bitline BL0 is transferred tothe page buffer 10 (i.e., the page buffering and sensing block 12)through the input/output line I/O0 when both of the column gatingsignals YA0 and YB0 are active with high levels. The amended data Dctemporarily stored in the latches are written into the transcript pagePGn-1 by way of a programming process. FIG. 6 shows a practical fashionof generating the new parities NP according to embodiments of thepresent invention. The old parities OP are previously stored in apredetermined field of the memory, which were made in a formerprogramming operation. Known techniques for generating parities arebriefly divided into two ways: one is a serial way and the other is aparallel way. Embodiments of the present invention employs the serialway in order to save a topological circuit area, but either embodimentis acceptable.

Illustrating that the source data De from which the parities areestablished is composed of 8-bits by 512-bytes, the parities areclassified into column parities and line parities. The column paritiesare obtained from the 8 bits of one byte, while the line parities fromthe 512 bytes.

The column and line parities can be made in the circuits shown in FIGS.7 and 8 respectively, both circuits being included in the paritygenerator 40 shown in FIG. 4. The generation of the column and lineparities is accomplished by conducting exclusive-OR (XOR) logic chainswith binary combinations to obtain a bit error from the packages of bitsor bytes.

Now will be described about creating the column parities from the eightbits b0˜b7 with reference to FIGS. 6 and 7 and Table 1 following.

TABLE 1 Arithmetic Combination Column Parity b7 b6 b5 b4 b3 b2 b1 b0CP1 * * * * nCP1 * * * * CP2 * * * * nCP2 * * * * CP4 * * * *nCP4 * * * * The letter “*” represents the XOR operator to obtain thecomparison result from the relevant bit combination. Therefore, completearithmetic equations of the XOR logic are summarized as follows each forthe column parities of six bits. CP1 = b7 * b5 * b3 * b1 nCP1 = b6 *b4 * b2 * b0 CP2 = b7 * b6 * b3 * b2 nCP2 = b5 * b4 * b1 * b0 CP4 = b7 *b6 * b5 * b4 nCP4 = b3 * b2 * b1 * b0

Referring to FIG. 7, implementing the arithmetic combinations togenerate each column parity is associated with four XOR gates XR and oneflipflop FF. Each input/output line corresponds to each data bit. Thecolumn parity nCP4 is generated from a flipflop FF6 receiving an outputof an XOR gate XR19. The gate XR19 receives an output of an XOR gateXR13 and the column parity nCP4 fed-back thereto from the flipflop FF6.The gate XR13 receives outputs of XOR gates XR1 and XR2. Theinput/output lines I/O2 and I/O3 are coupled to inputs of the gate XR2,while the input/output lines I/O0 and I/O1 to inputs of the gate XR1,The column parity CP4 complementary to the nCP4 is generated from aflipflop FF5 receiving an output of an XOR gate XR20. The gate XR20receives an output of an XOR gate XR14 and the column parity CP4fed-back thereto from the flipflop FF5. The gate XR14 receives outputsof XOR gates XR3 and XR4. The input/output lines I/O4 and I/O5 arecoupled to inputs of the gate XR3, while the input/output lines I/O6 andI/O7 to inputs of the gate XR4.

The column parity nCP2 is generated from a flipflop FF4 receiving anoutput of an XOR gate XR21. The gate XR21 receives an output of an XORgate XR 15 and the column parity nCP2 fed-back thereto from the flipflopFF4. The gate XR15 receives outputs of XOR gates XR5 and XR6. Theinput/output lines I/O0 and I/O1 are coupled to inputs of the gate XR5,while the input/output lines I/O4 and I/O5 to inputs of the gate XR6.The column parity CP2 complementary to the nCP2 is generated from aflipflop FF3 receiving an output of an XOR gate XR22. The gate XR22receives an output of an XOR gate XR16 and the column parity CP2fed-back thereto from the flipflop FF3. The gate XR16 receives outputsof XOR gates XR7 and XR8. The input/output lines I/O2 and I/O3 arecoupled to an input of the gate XR7, while the input/output lines I/O6and I/O7 to an input of the gate XR8.

The column parity nCP1 is generated from a flipflop FF2 receiving anoutput of an XOR gate XR23. The gate XR23 receives an output of an XORgate XR17 and the column parity nCP1 fed-back thereto from the flipflopFF2. The gate XR17 receives outputs of XOR gates XR9 and XR10. Theinput/output lines I/O0 and I/O2 are coupled to inputs of the gate XR9,while the input/output lines I/O4 and I/O6 to inputs of the gate XR10.The column parity CP1 complementary to the nCP2 is generated from aflipflop FF1 receiving an output of an XOR gate XR24. The gate XR24receives an output of an XOR gate XR18 and the column parity CP1fed-back thereto from the flipflop FF1. The gate XR18 receives outputsof XOR gates XR11 and XR12. The input/output lines I/O1 and I/O3 arecoupled to an input of the gate XR11, while the input/output lines I/O5and I/O7 to an input of the gate XR12.

A clock signal CLK and a reset signal RST are applied to the flipflopsFF1˜FF6 in common. Thus, the flipflops FF1˜FF6 outputs the columnparities in response to rising edges of every cycle of the clock signalCLK. the feedback input of each column parity to the XOR gate positionedbefore its corresponding flipflop (e.g., nCP4 to XR19 from FF6) isdirected to detect the variation between a current bit and the next bitin the source data (i.e., to detect a progressive bit error during thepage copy operation) and then to manage it with the serial way of paritygeneration.

As a practical example in the column parity generation, the columnparities CP1, CP2 and nCP4 will be set to “1”, provided the bit b3 is anerror bit.

The generation of the line parities from the 512 bytes will be describedwith reference to FIGS. 6 and 8 and the following Table 2. Table 2arranges byte combinations for XOR arithmetic implements in order toobtain the line parities LP1, nLP1, LP2, nLP2, LP4, nLP4, LP512, andnLP512 (LP1˜nLP512; 18 bits) against the 512 bytes of the source data.

TABLE 2 Arithmetic Combination {circumflex over ( )}B511 Line{circumflex over ( )}B510 {circumflex over ( )}B255 {circumflex over( )}B3 Parity {circumflex over ( )}B512 {circumflex over ( )}B509 . . .{circumflex over ( )}B256 {circumflex over ( )}B254 {circumflex over( )}B253 . . . {circumflex over ( )}B4 {circumflex over ( )}B2{circumflex over ( )}B1 LP1 * * . . . * * . . . * * nLP1 ** . . . * * .. . * * LP2 * * . . . * * . . . * * nLP2 ** . . . * * . . . * * LP4 **** . . . * ** * . . . nLP4 . . . . . . * ** * . . . . . . LP512 * *** .. . . . . nLP512 . . . * ** * . . . * ** *

In Table 2, the letter “*” notes the XOR operator to obtain thecomparison result from the relevant bit combination, and “̂B” representsa result of an XOR operation for eight bits of their corresponding byte(e.g., ̂B512=b7*b6*b5*b4*b3*b2*b1*b0 in the 512'th byte). The factor ̂13will be referred to as “byte parity unit” hereinafter.

Therefore, complete arithmetic equations of the XOR logic from Table 2are summarized as follows each for the line parities of 18 bits.

-   LP1=̂B512*̂B510* . . . *̂B256*̂B254* . . . *̂B4 *132-   nLP2=̂B511*̂B509* . . . *̂B255*̂B253* . . . *̂B3*̂B1-   LP2=̂B512 ̂B511* . . . *̂B256*̂B255* . . . *̂B4 ̂B3-   nLP2=̂B510*̂B509* . . . *̂B254*̂B253* . . . *̂B2*̂B1-   LP4=̂B512*̂B511*̂B510*̂B509* . . . *̂B256*̂B255*̂B254*̂B253 * . . . * ̂B8*̂B7    *̂B6*̂B5-   nLP4=̂B508*̂B507*̂B506*̂B505* . . . *̂B252*̂B251*̂B250*̂B249 *. . . * ̂B4*̂B3    *̂B2*̂B1-   LP512=̂B512*̂B511 *̂B510*̂B509* . . . * ̂B260*̂B259    -   *̂B258*̂B257-   nLP512=̂B256*̂B255 *̂B254*̂B253* . . . * ̂B4*̂B3    -   *̂B2*̂B1

Referring to FIG. 8, the byte parity unit ̂B for each byte is firstobtained through XOR gates XR31˜XR37. The byte parity unit ̂B isgenerated from the gate XR37. The gate XR37 receives outputs of thegates XR35 and XR36. The gate XR35 receives outputs of the gates XR31and XR32, and the gate XR36 receives outputs of the gates XR33 and XR34.Inputs of the gate XR31 are coupled to the input/output lines I/O0 andI/O1, and inputs of the gate XR32 are coupled to the input/output linesI/O2 and I/O3. Inputs of the gate XR33 are coupled to the input/outputlines I/O4 and I/O5, and inputs of the gate XR34 are coupled to theinput/output lines I/O6 and I/O7.

The output of the gate XR37, ̂B, is branched into 18 ways to establishthe 18 line parities LP1˜nLP512, being applied to inputs of NAND gatesND1˜ND18 in common. If there is an error bit among the eight bits oftheir corresponding byte, the byte parity unit ̂B is set to “1”. TheNAND gates ND1˜ND18 respond each to clock control signals nCLK1, CLK1,nCLK2, CLK2, . . . , nCLK512, and CLK512 (nCLK1˜CLK512; 18 ea) tocontrol bit paths from the byte parity unit ̂B to the line parities.Outputs of the NAND gates ND1˜ND18 are applied to inputs of XOR gatesXR1˜XR18 respectively. The gates XR1˜XR18 also receive the line paritiesnLP1˜LP18 fed-back thereto from flipflops FF1˜FF18 receiving outputs ofthe gates XR1˜XR18, respectively.

As the clock signal CLK and the reset signal RST are applied to theflipflops FF1˜FF18 in common, the flipflops FF1˜FF18 outputs the lineparities in response to rising edges of every cycle of the clock signalCLK. The feedback input of each column parity to the XOR gate positionedbefore its corresponding flipflop (e.g., LP512 to XR1018 from FF1018) isdirected to detect the variation between a current bit and the next bitin the source data (i.e., to detect a progressive bit error during thepage copy operation) and then to manage it with the serial way of lineparity generation. As a practical example in the line parity generation,if the byte B3 has an error bit, the line parities nLP1, LP2, nLP4, . .. , nLP512 will be set to “1”.

The timing diagram of FIG. 9 shows pulsing states of the column gatingsignals and clock control signals for transferring the source data fromthe page buffer 10 to the error correction circuit 20, associated withthe operations in the circuits of FIGS. 4 through 8. The transmissionprocedure shown in FIG. 9 is exemplarily carried out by way of thelatching and column-decoding block LDB1 shown in FIG. 4.

Referring to FIG. 9, as the primary column gating signals YA0˜YAn-1 aresuccessively active with high levels for the secondary column gatingsignal YB0 is being enabled with a high level, data bits correspondingto the bitlines BL0˜BLn-1 are sequentially transferred to the errorcorrection circuit 20 through their corresponding input/output linesI/O0˜I/On-1. By the same manner, in accordance with the sequentialactivation of the primary column gating signals YA0˜YAn-1 for eachactive state of the secondary column gating signals YB0˜YBk-1, all the512 bytes of the source data are transferred to the error correctioncircuit 20 through the input/output lines I/O0˜I/On-1.

In the error correction circuit 20, responding to the periodicoscillation of the clock signal CLK, the flipflops FF1˜FF6 of the columnparity generator shown in FIG. 7 output the column parities CP1˜nCP4. Atthe same time, the clock control signals CLK1˜nCLK512 demultiplied fromthe clock signal CLK enable the bit paths to be conductive through theNAND gates ND1˜ND18 of the line parity generator shown in FIG. 8, andthe flipflops FF1˜FF18 of the line parity generator outputs the lineparities LP1˜nLP512 of 18 bits.

The bit number of the new parities NP is 24 that is composed of theeight column parities CP1˜nCP4 and the eighteen line paritiesLP1˜nLP512, which is the same with the old parities OP that have beenstored in a predetermined field of the flash memory.

An overall sequence for carry out the page copy operation with the errorcorrection is as follows.

First, the old parities OP are generated and stored in a predeterminedfield of the memory during a programming period. After then, the newparities NP are generated by the circuits and procedure aforementionedas shown in FIGS. 6 through 8. The old and new parities are comparedfrom each other by 24 bits.

In comparing the old parities OP with the new parities NP by the paritycomparator 50, if all 24 bits of the old and new parities are identical(i.e., the XOR operations with the old and new parities result in “0”),it is regarded as no error bit. On the other hand, it is regarded asone-bit error when the comparison result is “1” for 12 bits (a half ofthe 24 bits) between the old and new parities. Such a one-bit error iscured by the correction logic circuit 60. Otherwise, only a comparisonresult for one bit among the 24 bits becomes “1”, it is regarded as asingle error that has been already contained in the source data of thepage to be copied. Other case except the former cases of comparisonresults may be regarded as there are more than two error bits.

Such bit error conditions may be available to be identified by a user inresponse to a command. Further, it may be practicable to transcribe theamended data into the source page as well as the transcription page.

The error correction circuit may be embedded in the flash memoryaccording to embodiments of the present invention.

As described above, since an error bit contained in the source data of asource page is detected and cured by the error correction circuit beforebeing written into a transcription page, it prevents the error bit ofthe source data from being transcribed into the transcription page.

Moreover, the flash memory according to present invention efficientlyeliminates a progressive bit error that could occur during a page copyoperation.

And, according to the embodiment aforementioned, there is no need ofbuffering components for error correction during a page copy operationbecause the page buffer, which is basically employed in a normal flashmemory, is efficiently usable to assist the operation without additionalmodifications.

Although the preferred embodiments of the present invention have beendisclosed for illustrative purposes, those skilled in the art willappreciate that various modifications, additions and substitutions arepossible, without departing from the scope and spirit of the inventionas described in the accompanying claims.

1. A nonvolatile memory comprising: a plurality of pages storing data; apage buffer temporarily storing data by the page; a correction circuitfor correcting a bit error of source data of a specific one of thepages; a transferring circuit configured to provide the source data tothe correction circuit from the page buffer and to provide amended datato the page buffer from the correction circuit after the correctioncircuit has corrected the bit error; and a replicating circuitconfigured to copy the source data into the page buffer and to store theamended data into another page from the page buffer; wherein: the sourcedata contains old parities; the correction circuit for generating newparities from the source data, and compares the new parities with theold parities; the correction circuit comprises a circuit for generatingcolumn parities for bits composing one byte of the source data; and acircuit for generating line parities for bytes of the source data; andfor a one bit error in the source data, the line parities indicate abinary weighted line address and its complement of the one bit error inthe page buffer, and the column parities indicate a binary weightedcolumn address and its complement of the one bit error in the pagebuffer.
 2. The nonvolatile memory of claim 1, wherein the nonvolatilememory is a NAND flash memory.
 3. A nonvolatile memory comprising: adata field composed of a plurality of pages for storing data; a firststorage configured to store first parities in a predetermined region ofthe data field, the first parities being generated during a programmingoperation for the page; a page buffer for temporarily storing data bythe page; a moving circuit configured to copy source data stored in afirst one of the pages into the page buffer; a parity circuit configuredto generate second parities from the source data stored in the pagebuffer; a correction circuit configured to generate modified data fromthe source data in response to a result of comparing the first paritieswith the second parities; and a transfer circuit configured to transferthe modified data of the source data to the page buffer; wherein: themoving circuit is further configured to copy the modified data in thepage buffer to a second one of the pages after the correction circuithas generated the modified data; the parity circuit comprises a circuitfor generating column parities for bits composing one byte of the sourcedata; and a circuit for generating line parities for bytes of the sourcedata; and for a one bit error in the source data, the line paritiesindicate a binary weighted line address and its complement of the onebit error in the page buffer, and the column parities indicate a binaryweighted column address and its complement of the one bit error in thepage buffer.
 4. The nonvolatile memory of claim 3, wherein the secondparities comprise column parities and line parities.
 5. The nonvolatilememory of claim 4, wherein the parity circuit comprises a circuit forgenerating column parities for bits composing one byte of the sourcedata; and a circuit for generating line parities for bytes of the sourcedata.
 6. The nonvolatile memory of claim 3, wherein the nonvolatilememory is a NAND flash memory.
 7. A method of transferring source dataof a first page to a second page in a nonvolatile memory having a pagebuffer structured to temporarily store data by the page, the source datacontaining old parities, the method comprising: storing the source datafrom the first page into the page buffer; generating new parities fromthe source data stored in the page buffer; comparing the old paritieswith the new parities; creating modified data from the source data inresponse to a result of the comparing; moving the modified data to thepage buffer after the creation of the modified data; and storing themodified data in the page buffer in the second page; wherein: storingthe source data into the page buffer further comprises storing thesource data into a plurality of lines and a plurality of columns of thepage buffer; and generating new parities from the source data stored inthe page buffer further comprises generating the new parities including:a plurality of pairs of line parities, for each line parity pair, afirst line parity associated with a first half of the lines, and asecond line parity associated with a second half of the lines; and aplurality of pairs of column parities, for each column parity pair, afirst column parity of the pair associated with a first half of thecolumns, and a second column parity of the pair associated with a secondhalf of the columns; wherein for a one bit error in the source data, theline parities indicate a binary weighted line address and its complementof the one bit error in the page buffer, and the column paritiesindicate a binary weighted column address and its complement of the onebit error in the page buffer.
 8. The method of claim 7, furthercomprising storing the old parities of the source data into apredetermined field of the memory before storing the source data intothe page buffer.
 9. The method of claim 7, further comprising informingan error status by the comparing result of the outside of the memory.